42 lines
No EOL
665 B
Verilog
42 lines
No EOL
665 B
Verilog
module jyh_4490_5_divider(clk_out,sel,clk,en);
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input clk,sel,en;
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output reg clk_out;
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reg [14:0]counter=0;
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localparam TARGET_4=2784; // ((1/4490)/(1/50M))/4
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localparam TARGET_5=863; // ((1/14490)/(1/50M))/4
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initial begin
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clk_out=0;
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end
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always @(posedge clk)
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if(en)
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begin
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counter<=counter+1;
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if(sel)
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begin
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if(counter==TARGET_5)
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begin
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clk_out<=0;
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end
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if(counter==4*TARGET_5)
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begin
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clk_out<=1;
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counter<=0;
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end
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end
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else if(!sel)
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begin
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if(counter==TARGET_4)
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begin
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clk_out<=0;
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end
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if(counter==4*TARGET_4)
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begin
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clk_out<=1;
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counter<=0;
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end
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end
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end
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endmodule |