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justhomework/Quartus/UART_Design/uart_screen/uart_screen_bb.v
2022-06-25 17:00:22 +08:00

28 lines
658 B
Verilog

module uart_screen (
clk_clk,
reset_reset_n,
rs232_0_from_uart_ready,
rs232_0_from_uart_data,
rs232_0_from_uart_error,
rs232_0_from_uart_valid,
rs232_0_to_uart_data,
rs232_0_to_uart_error,
rs232_0_to_uart_valid,
rs232_0_to_uart_ready,
rs232_0_UART_RXD,
rs232_0_UART_TXD);
input clk_clk;
input reset_reset_n;
input rs232_0_from_uart_ready;
output [7:0] rs232_0_from_uart_data;
output rs232_0_from_uart_error;
output rs232_0_from_uart_valid;
input [7:0] rs232_0_to_uart_data;
input rs232_0_to_uart_error;
input rs232_0_to_uart_valid;
output rs232_0_to_uart_ready;
input rs232_0_UART_RXD;
output rs232_0_UART_TXD;
endmodule