15 lines
179 B
Verilog
15 lines
179 B
Verilog
module jyh_4490_3_divide(clkin,clkout);
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input clkin;
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output reg clkout=0;
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reg [2:0] temp;
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always@(posedge clkin)
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begin
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temp<=temp+1;
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if(temp==0)
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clkout=~clkout;
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end
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endmodule
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