23 lines
No EOL
470 B
Verilog
23 lines
No EOL
470 B
Verilog
module jyh_4490_1(codeout,indec);
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input[3:0] indec;
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output[6:0] codeout;
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reg[6:0] codeout;
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always @ (indec)
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begin
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case (indec)
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4'd0: codeout=7'b1111110;
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4'd1: codeout=7'b0110000;
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4'd2: codeout=7'b1101101;
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4'd3: codeout=7'b1111001;
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4'd4: codeout=7'b0110011;
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4'd5: codeout=7'b1011011;
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4'd6: codeout=7'b1011111;
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4'd7: codeout=7'b1110000;
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4'd8: codeout=7'b1111111;
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4'd9: codeout=7'b1111011;
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default: codeout=7'bx;
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endcase
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end
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endmodule |