18 lines
No EOL
351 B
Verilog
18 lines
No EOL
351 B
Verilog
module jyh_4490_4_divider(clk,clk_out);
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input clk;
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output reg clk_out;
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localparam TARGET=2;
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reg [15:0]counter=0;
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initial begin
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clk_out=0;
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end
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always @(posedge clk)
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begin
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counter=counter+1;
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if(counter==TARGET)
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begin
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counter=0;
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clk_out=!clk_out;
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end
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end
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endmodule |