21 lines
No EOL
220 B
Verilog
21 lines
No EOL
220 B
Verilog
//计数器模块
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module jyh_4490_2_1(clk,en,Q);
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input clk,en;
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output reg[2:0] Q;
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always@(posedge clk)
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begin
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if(en == 1'b1)
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begin
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if(Q<3'd6)
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Q <= Q + 1'b1;
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else
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Q <= 0;
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end
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else
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Q<=0;
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end
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endmodule
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