28 lines
658 B
Verilog
28 lines
658 B
Verilog
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module uart_screen (
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clk_clk,
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reset_reset_n,
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rs232_0_from_uart_ready,
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rs232_0_from_uart_data,
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rs232_0_from_uart_error,
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rs232_0_from_uart_valid,
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rs232_0_to_uart_data,
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rs232_0_to_uart_error,
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rs232_0_to_uart_valid,
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rs232_0_to_uart_ready,
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rs232_0_UART_RXD,
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rs232_0_UART_TXD);
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input clk_clk;
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input reset_reset_n;
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input rs232_0_from_uart_ready;
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output [7:0] rs232_0_from_uart_data;
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output rs232_0_from_uart_error;
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output rs232_0_from_uart_valid;
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input [7:0] rs232_0_to_uart_data;
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input rs232_0_to_uart_error;
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input rs232_0_to_uart_valid;
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output rs232_0_to_uart_ready;
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input rs232_0_UART_RXD;
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output rs232_0_UART_TXD;
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endmodule
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