24 lines
No EOL
274 B
Verilog
24 lines
No EOL
274 B
Verilog
`timescale 1ns/1ns
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module jyh_4490_5_testbench;
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reg clk;
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reg en;
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wire clk_out;
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reg sel;
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initial begin
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clk=0;
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sel=0;
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en=0;
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#100
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en=1;
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end
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always#10 clk=~clk;
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always#50000000 sel=~sel;
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jyh_4490_5_divider D1(
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.en(en),
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.sel(sel),
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.clk_out(clk_out),
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.clk(clk)
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);
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endmodule |