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justhomework/Quartus/v6_testbench/transcript
2022-06-13 17:46:38 +08:00

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vsim work.jyh_4490_6_testbench
# vsim work.jyh_4490_6_testbench
# Start time: 13:05:56 on Jun 08,2022
# Loading work.jyh_4490_6_testbench
# Loading work.jyh_4490_mstate
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'M1'. Expected 5, found 4.
# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 40
# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v(40): [TFMPC] - Missing connection for port 'en'.
add wave -position end sim:/jyh_4490_6_testbench/clk
add wave -position end sim:/jyh_4490_6_testbench/in
add wave -position end sim:/jyh_4490_6_testbench/en
add wave -position end sim:/jyh_4490_6_testbench/out
run -continue
run -all
# Break key hit
# Break in Module jyh_4490_6_testbench at /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v line 15
# End time: 13:06:58 on Jun 08,2022, Elapsed time: 0:01:02
# Errors: 0, Warnings: 4