14 lines
469 B
Text
14 lines
469 B
Text
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# Compile of jyh_4490_5_divider.v was successful.
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vsim work.jyh_4490_5_testbench
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# vsim work.jyh_4490_5_testbench
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# Start time: 21:31:49 on Apr 19,2022
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# Loading work.jyh_4490_5_testbench
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# Loading work.jyh_4490_5_divider
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add wave -position end sim:/jyh_4490_5_testbench/clk
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add wave -position end sim:/jyh_4490_5_testbench/en
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add wave -position end sim:/jyh_4490_5_testbench/sel
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add wave -position end sim:/jyh_4490_5_testbench/clk_out
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run -continue
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run -all
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run
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