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justhomework/Quartus/v6/jyh_4490_6_testbench.v

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2022-05-09 16:05:40 +00:00
`timescale 1ns/1ns
module jyh_4490_6_testbench;
reg clk;
reg in;
reg en;
wire out;
wire [19:0] cnt;
initial begin
clk=0;
in=0;
en=1;
end
always#10 clk=~clk;
always#20000000
begin
in=0;
repeat(5)
begin
in=1;
#1000000;
in=0;
#1000000;
end
in=1;
#35000000
repeat(5)
begin
in=0;
#1000000;
in=1;
#1000000;
end
in=0;
end
jyh_4490_mstate M1(
.clk(clk),
.in(in),
.out(out),
.cnt(cnt));
endmodule