44 lines
No EOL
421 B
Verilog
44 lines
No EOL
421 B
Verilog
`timescale 1ns/1ns
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module jyh_4490_6_testbench;
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reg clk;
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reg in;
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reg en;
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wire out;
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wire [19:0] cnt;
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initial begin
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clk=0;
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in=0;
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en=1;
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end
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always#10 clk=~clk;
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always#20000000
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begin
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in=0;
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repeat(5)
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begin
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in=1;
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#1000000;
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in=0;
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#1000000;
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end
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in=1;
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#35000000
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repeat(5)
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begin
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in=0;
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#1000000;
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in=1;
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#1000000;
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end
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in=0;
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end
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jyh_4490_mstate M1(
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.clk(clk),
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.in(in),
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.out(out),
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.cnt(cnt));
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endmodule |