实验性代码

This commit is contained in:
iridiumR 2022-04-12 17:03:50 +08:00
parent 130d8e43d5
commit 2136c95225
6 changed files with 1419 additions and 33 deletions

1310
Quartus/v4/Waveform.vwf Normal file

File diff suppressed because it is too large Load diff

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@ -0,0 +1,61 @@
BANDWIDTH_TYPE=AUTO
CLK0_DIVIDE_BY=1
CLK0_DUTY_CYCLE=50
CLK0_MULTIPLY_BY=1
CLK0_PHASE_SHIFT=0
COMPENSATE_CLOCK=CLK0
INCLK0_INPUT_FREQUENCY=166666
INTENDED_DEVICE_FAMILY="Cyclone IV E"
LPM_TYPE=altpll
OPERATION_MODE=NORMAL
PLL_TYPE=AUTO
PORT_ACTIVECLOCK=PORT_UNUSED
PORT_ARESET=PORT_USED
PORT_CLKBAD0=PORT_UNUSED
PORT_CLKBAD1=PORT_UNUSED
PORT_CLKLOSS=PORT_UNUSED
PORT_CLKSWITCH=PORT_UNUSED
PORT_CONFIGUPDATE=PORT_UNUSED
PORT_FBIN=PORT_UNUSED
PORT_INCLK0=PORT_USED
PORT_INCLK1=PORT_UNUSED
PORT_LOCKED=PORT_USED
PORT_PFDENA=PORT_UNUSED
PORT_PHASECOUNTERSELECT=PORT_UNUSED
PORT_PHASEDONE=PORT_UNUSED
PORT_PHASESTEP=PORT_UNUSED
PORT_PHASEUPDOWN=PORT_UNUSED
PORT_PLLENA=PORT_UNUSED
PORT_SCANACLR=PORT_UNUSED
PORT_SCANCLK=PORT_UNUSED
PORT_SCANCLKENA=PORT_UNUSED
PORT_SCANDATA=PORT_UNUSED
PORT_SCANDATAOUT=PORT_UNUSED
PORT_SCANDONE=PORT_UNUSED
PORT_SCANREAD=PORT_UNUSED
PORT_SCANWRITE=PORT_UNUSED
PORT_clk0=PORT_USED
PORT_clk1=PORT_UNUSED
PORT_clk2=PORT_UNUSED
PORT_clk3=PORT_UNUSED
PORT_clk4=PORT_UNUSED
PORT_clk5=PORT_UNUSED
PORT_clkena0=PORT_UNUSED
PORT_clkena1=PORT_UNUSED
PORT_clkena2=PORT_UNUSED
PORT_clkena3=PORT_UNUSED
PORT_clkena4=PORT_UNUSED
PORT_clkena5=PORT_UNUSED
PORT_extclk0=PORT_UNUSED
PORT_extclk1=PORT_UNUSED
PORT_extclk2=PORT_UNUSED
PORT_extclk3=PORT_UNUSED
SELF_RESET_ON_LOSS_LOCK=OFF
WIDTH_CLOCK=5
DEVICE_FAMILY="Cyclone IV E"
CBX_AUTO_BLACKBOX=ALL
areset
inclk
inclk
clk
locked

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@ -55,4 +55,6 @@ set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE jyh_4490_4_divider.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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@ -0,0 +1,18 @@
module jyh_4490_4_divider(clk,clk_out);
input clk;
output reg clk_out;
localparam TARGET=2;
reg [15:0]counter=0;
initial begin
clk_out=0;
end
always @(posedge clk)
begin
counter=counter+1;
if(counter==TARGET)
begin
counter=0;
clk_out=!clk_out;
end
end
endmodule

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@ -1,8 +1,8 @@
//七段四位译码器 //七段四位译码器
module jyh_4490_4_encoder(sel,codeout,clk, d1, d2); module jyh_4490_4_encoder(sel,codeout,clk, d1, d2, d3, d4);
input clk; input clk;
input [6:0] d1, d2; input [6:0] d1, d2, d3, d4;
output reg [1:0] sel; //位选 output reg [3:0] sel; //位选
output reg [6:0] codeout; //型码 output reg [6:0] codeout; //型码
@ -21,10 +21,14 @@ begin
else else
begin begin
isEnable<=1; isEnable<=1;
if(loc==2'b01) if(loc==4'b01)
loc=2'b10; loc=4'b10;
else else if(loc==4'b10)
loc=2'b01; loc=4'b100;
else if(loc==4'b100)
loc=4'b1000;
else if(loc==4'b1000)
loc=4'b1;
end end
end end
@ -33,8 +37,10 @@ begin
if(isEnable) if(isEnable)
begin begin
case (loc) case (loc)
2'b01: begin code_loc = d1; sel = 4'b10; end 4'b0001: begin code_loc = d1; sel = 4'b0001; end
2'b10: begin code_loc = d2; sel = 4'b01; end 4'b0010: begin code_loc = d2; sel = 4'b0010; end
4'b0100: begin code_loc = d2; sel = 4'b0100; end
4'b1000: begin code_loc = d2; sel = 4'b1000; end
endcase endcase
end end
end end

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@ -1,7 +1,7 @@
module jyh_4490_4_entry(out1, out0, code, sel, CO, module jyh_4490_4_entry(out1, out0, code, sel, CO,
// 十位输出 个位输出 数码管型码 数码管位码 /借位标志位 // 十位输出 个位输出 数码管型码 数码管位码 /借位标志位
in1, in0, load, clk, clr, en, upd); in1, in0, load, clk, subclk, clr, en, upd);
// 十位装载 个位装载 装载信号 计数时钟信号 清零信号 使能信号 正反计数标志位 // 十位装载 个位装载 装载信号 计数时钟信号 分频信号 清零信号 使能信号 正反计数标志位
output [3:0] out1; output [3:0] out1;
output [3:0] out0; output [3:0] out0;
@ -13,17 +13,17 @@ input [3:0] in0;
input clk,load,clr,en,upd; input clk,load,clr,en,upd;
//wire subclk; output subclk;
//jyh_4490_3_divide( jyh_4490_4_divider D1(
//.clkin(clk), .clk(clk),
//.clkout(subclk) .clk_out(subclk)
//); );
//个位计数器 //个位计数器
jyh_4490_4_counter c0( jyh_4490_4_counter C1(
.Q(out0), .Q(out0),
.clk(clk), .clk(subclk),
.co(CO), .co(CO),
.clr(clr), .clr(clr),
.load(load), .load(load),
@ -32,31 +32,20 @@ jyh_4490_4_counter c0(
.upd(upd)); .upd(upd));
//十位计数器 //十位计数器
jyh_4490_4_counter c1( jyh_4490_4_counter C2(
.Q(out1), .Q(out1),
.clk(CO||load), .clk(CO||load),
.clr(clr), .clr(clr),
.load(load), .load(load),
.in(in1),
.en(en), .en(en),
.upd(upd)); .upd(upd));
//四位数码管译码器 //四位数码管译码器
//jyh_4490_3_encoder e1( jyh_4490_4_encoder E1(
//.codeout(code),
//.d1(out0),
//.d2(out1),
//.clk(clk),
//.sel(sel[1:0])
//);
jyh_4490_4_simpleEncoder e1(
.codeout(code), .codeout(code),
.d1(out0), .d1(out0),
.d2(out1),
.clk(clk), .clk(clk),
.sel(sel[0:0]) .sel(sel[3:0])
); );
endmodule endmodule