ir
/
justhomework
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

修复bug

This commit is contained in:
iridiumR 2022-04-19 15:19:04 +08:00
parent 61cc77b855
commit 5595711307
4 changed files with 422 additions and 436 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

838
Quartus/v4/Waveform.vwf
View File

File diff suppressed because it is too large Load Diff

14
Quartus/v4/jyh_4490_4.qsf
View File

@ -56,8 +56,7 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE jyh_4490_4_divider.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_location_assignment PIN_43 -to CO
set_location_assignment PIN_58 -to CO
set_location_assignment PIN_89 -to clk
set_location_assignment PIN_24 -to clr
set_location_assignment PIN_103 -to code[0]
@ -77,7 +76,6 @@ set_location_assignment PIN_46 -to out0[0]
set_location_assignment PIN_50 -to out0[1]
set_location_assignment PIN_52 -to out0[2]
set_location_assignment PIN_54 -to out0[3]
set_location_assignment PIN_58 -to out1[0]
set_location_assignment PIN_53 -to out1[1]
set_location_assignment PIN_51 -to out1[2]
set_location_assignment PIN_49 -to out1[3]
@ -91,4 +89,14 @@ set_location_assignment PIN_113 -to seg[6]
set_location_assignment PIN_120 -to seg[7]
set_location_assignment PIN_30 -to upd
set_location_assignment PIN_90 -to clk_50m
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
Quartus/v4/jyh_4490_4_counter.v
View File

@ -62,8 +62,6 @@ begin
end
end
end
else
Q<=0;
end
endmodule

4
Quartus/v4/jyh_4490_4_divider.v
View File

@ -1,8 +1,8 @@
module jyh_4490_4_divider(clk,clk_out);
input clk;
output reg clk_out;
// localparam TARGET=100000;
localparam TARGET=1;
localparam TARGET=50000;
// localparam TARGET=1;
reg [19:0]counter=0;
initial begin
clk_out=0;