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暂且不知道这堆东西能不能用

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This commit is contained in:
iridiumR 2022-05-28 00:35:55 +08:00
parent a17a2e0ff1
commit 87df93e775
48 changed files with 13732 additions and 0 deletions
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2260
Quartus/Design/.qsys_edit/UART.xml Normal file
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14
Quartus/Design/.qsys_edit/UART_schematic.nlv Normal file
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
#
preplace inst UART -pg 1 -lvl 1 -y 40 -regy -20
preplace inst UART.rs232_0 -pg 1 -lvl 1 -y 100
preplace inst UART.clk_0 -pg 1 -lvl 1 -y 30
preplace netloc EXPORT<net_container>UART</net_container>(SLAVE)UART.reset,(SLAVE)clk_0.clk_in_reset) 1 0 1 NJ
preplace netloc EXPORT<net_container>UART</net_container>(SLAVE)UART.rs232_0_external_interface,(SLAVE)rs232_0.external_interface) 1 0 1 NJ
preplace netloc EXPORT<net_container>UART</net_container>(SLAVE)UART.clk,(SLAVE)clk_0.clk_in) 1 0 1 NJ
preplace netloc EXPORT<net_container>UART</net_container>(SLAVE)rs232_0.clk,(SLAVE)UART.rs232_0_clk) 1 0 1 NJ
preplace netloc EXPORT<net_container>UART</net_container>(SLAVE)UART.rs232_0_reset,(SLAVE)rs232_0.reset) 1 0 1 NJ
preplace netloc EXPORT<net_container>UART</net_container>(MASTER)UART.rs232_0_avalon_data_receive_source,(MASTER)rs232_0.avalon_data_receive_source) 1 1 1 N
preplace netloc EXPORT<net_container>UART</net_container>(SLAVE)UART.rs232_0_avalon_data_transmit_sink,(SLAVE)rs232_0.avalon_data_transmit_sink) 1 0 1 NJ
levelinfo -pg 1 0 200 680
levelinfo -hier UART 210 240 460

2
Quartus/Design/.qsys_edit/filters.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<filters version="21.1" />

14
Quartus/Design/.qsys_edit/preferences.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
<connections preferredWidth="79" />
<irq preferredWidth="34" />
</columns>
</systemtable>
<library
expandedCategories="Library/Interface Protocols/Ethernet/Reference Design Components,Library/University Program,Library/University Program/Clock,Library/Basic Functions/Simulation; Debug and Verification/Simulation,Library/Interface Protocols/Audio &amp; Video,Library,Project,Library/Interface Protocols/Ethernet,Library/University Program/Audio &amp; Video,Library/Basic Functions/Bridges and Adaptors/Clock,Library/Qsys Interconnect/Interrupt,Library/Basic Functions,Library/DSP,Library/University Program/Audio &amp; Video/Video,Library/Basic Functions/Simulation; Debug and Verification,Library/Basic Functions/Bridges and Adaptors/Memory Mapped,Library/Basic Functions/Bridges and Adaptors,Library/Qsys Interconnect/Memory-Mapped Alpha,Library/Basic Functions/Clocks; PLLs and Resets,Library/Qsys Interconnect,Library/Interface Protocols,Library/Basic Functions/On Chip Memory,Library/DSP/Video and Image Processing" />
<window width="1313" height="756" x="542" y="384" />
<hdlexample language="VERILOG" />
</preferences>

2208
Quartus/Design/.qsys_edit/uart_screen.xml Normal file
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Quartus/Design/.qsys_edit/uart_screen_schematic.nlv Normal file
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
#
preplace inst unsaved.rs232_0 -pg 1 -lvl 1 -y 30
preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20
preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.clk,(SLAVE)rs232_0.clk) 1 0 1 NJ
preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.interrupt,(SLAVE)rs232_0.interrupt) 1 0 1 NJ
preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.reset,(SLAVE)rs232_0.reset) 1 0 1 NJ
preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.avalon_rs232_slave,(SLAVE)rs232_0.avalon_rs232_slave) 1 0 1 NJ
preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.external_interface,(SLAVE)rs232_0.external_interface) 1 0 1 NJ
levelinfo -pg 1 0 120 320
levelinfo -hier unsaved 130 160 310

1057
Quartus/Design/UART.sopcinfo Normal file
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171
Quartus/Design/UART/UART.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2021 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 544 368)
(text "UART" (rect 255 -1 284 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 352 20 364)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 224 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 224 112)(line_width 1))
)
(port
(pt 544 72)
(input)
(text "rs232_0_from_uart_ready" (rect 0 0 109 12)(font "Arial" (font_size 8)))
(text "rs232_0_from_uart_ready" (rect 410 61 548 72)(font "Arial" (font_size 8)))
(line (pt 544 72)(pt 304 72)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "rs232_0_to_uart_data[7..0]" (rect 0 0 109 12)(font "Arial" (font_size 8)))
(text "rs232_0_to_uart_data[7..0]" (rect 4 141 160 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 224 152)(line_width 3))
)
(port
(pt 0 168)
(input)
(text "rs232_0_to_uart_error" (rect 0 0 93 12)(font "Arial" (font_size 8)))
(text "rs232_0_to_uart_error" (rect 4 157 130 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 224 168)(line_width 1))
)
(port
(pt 0 184)
(input)
(text "rs232_0_to_uart_valid" (rect 0 0 90 12)(font "Arial" (font_size 8)))
(text "rs232_0_to_uart_valid" (rect 4 173 130 184)(font "Arial" (font_size 8)))
(line (pt 0 184)(pt 224 184)(line_width 1))
)
(port
(pt 0 240)
(input)
(text "rs232_0_clk" (rect 0 0 49 12)(font "Arial" (font_size 8)))
(text "rs232_0_clk" (rect 4 229 70 240)(font "Arial" (font_size 8)))
(line (pt 0 240)(pt 224 240)(line_width 1))
)
(port
(pt 0 280)
(input)
(text "rs232_0_UART_RXD" (rect 0 0 95 12)(font "Arial" (font_size 8)))
(text "rs232_0_UART_RXD" (rect 4 269 100 280)(font "Arial" (font_size 8)))
(line (pt 0 280)(pt 224 280)(line_width 1))
)
(port
(pt 0 336)
(input)
(text "rs232_0_reset" (rect 0 0 59 12)(font "Arial" (font_size 8)))
(text "rs232_0_reset" (rect 4 325 82 336)(font "Arial" (font_size 8)))
(line (pt 0 336)(pt 224 336)(line_width 1))
)
(port
(pt 544 88)
(output)
(text "rs232_0_from_uart_data[7..0]" (rect 0 0 122 12)(font "Arial" (font_size 8)))
(text "rs232_0_from_uart_data[7..0]" (rect 393 77 561 88)(font "Arial" (font_size 8)))
(line (pt 544 88)(pt 304 88)(line_width 3))
)
(port
(pt 544 104)
(output)
(text "rs232_0_from_uart_error" (rect 0 0 106 12)(font "Arial" (font_size 8)))
(text "rs232_0_from_uart_error" (rect 414 93 552 104)(font "Arial" (font_size 8)))
(line (pt 544 104)(pt 304 104)(line_width 1))
)
(port
(pt 544 120)
(output)
(text "rs232_0_from_uart_valid" (rect 0 0 103 12)(font "Arial" (font_size 8)))
(text "rs232_0_from_uart_valid" (rect 416 109 554 120)(font "Arial" (font_size 8)))
(line (pt 544 120)(pt 304 120)(line_width 1))
)
(port
(pt 0 200)
(output)
(text "rs232_0_to_uart_ready" (rect 0 0 96 12)(font "Arial" (font_size 8)))
(text "rs232_0_to_uart_ready" (rect 4 189 130 200)(font "Arial" (font_size 8)))
(line (pt 0 200)(pt 224 200)(line_width 1))
)
(port
(pt 0 296)
(output)
(text "rs232_0_UART_TXD" (rect 0 0 93 12)(font "Arial" (font_size 8)))
(text "rs232_0_UART_TXD" (rect 4 285 100 296)(font "Arial" (font_size 8)))
(line (pt 0 296)(pt 224 296)(line_width 1))
)
(drawing
(text "clk" (rect 209 43 436 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 229 67 476 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 195 83 420 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 229 107 500 224)(font "Arial" (color 0 0 0)))
(text "rs232_0_avalon_data_receive_source" (rect 305 43 814 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "ready" (rect 276 67 582 144)(font "Arial" (color 0 0 0)))
(text "data" (rect 283 83 590 176)(font "Arial" (color 0 0 0)))
(text "error" (rect 279 99 588 208)(font "Arial" (color 0 0 0)))
(text "valid" (rect 281 115 592 240)(font "Arial" (color 0 0 0)))
(text "rs232_0_avalon_data_transmit_sink" (rect 11 123 220 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "data" (rect 229 147 482 304)(font "Arial" (color 0 0 0)))
(text "error" (rect 229 163 488 336)(font "Arial" (color 0 0 0)))
(text "valid" (rect 229 179 488 368)(font "Arial" (color 0 0 0)))
(text "ready" (rect 229 195 488 400)(font "Arial" (color 0 0 0)))
(text "rs232_0_clk" (rect 153 211 372 435)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 229 235 476 480)(font "Arial" (color 0 0 0)))
(text "rs232_0_external_interface" (rect 64 251 284 515)(font "Arial" (color 128 0 0)(font_size 9)))
(text "RXD" (rect 229 275 476 560)(font "Arial" (color 0 0 0)))
(text "TXD" (rect 229 291 476 592)(font "Arial" (color 0 0 0)))
(text "rs232_0_reset" (rect 139 307 356 627)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 229 331 488 672)(font "Arial" (color 0 0 0)))
(text " UART " (rect 512 352 1060 714)(font "Arial" ))
(line (pt 224 32)(pt 304 32)(line_width 1))
(line (pt 304 32)(pt 304 352)(line_width 1))
(line (pt 224 352)(pt 304 352)(line_width 1))
(line (pt 224 32)(pt 224 352)(line_width 1))
(line (pt 225 52)(pt 225 76)(line_width 1))
(line (pt 226 52)(pt 226 76)(line_width 1))
(line (pt 225 92)(pt 225 116)(line_width 1))
(line (pt 226 92)(pt 226 116)(line_width 1))
(line (pt 303 52)(pt 303 124)(line_width 1))
(line (pt 302 52)(pt 302 124)(line_width 1))
(line (pt 225 132)(pt 225 204)(line_width 1))
(line (pt 226 132)(pt 226 204)(line_width 1))
(line (pt 225 220)(pt 225 244)(line_width 1))
(line (pt 226 220)(pt 226 244)(line_width 1))
(line (pt 225 260)(pt 225 300)(line_width 1))
(line (pt 226 260)(pt 226 300)(line_width 1))
(line (pt 225 316)(pt 225 340)(line_width 1))
(line (pt 226 316)(pt 226 340)(line_width 1))
(line (pt 0 0)(pt 544 0)(line_width 1))
(line (pt 544 0)(pt 544 368)(line_width 1))
(line (pt 0 368)(pt 544 368)(line_width 1))
(line (pt 0 0)(pt 0 368)(line_width 1))
)
)

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Quartus/Design/UART/UART.cmp Normal file
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component UART is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
rs232_0_from_uart_ready : in std_logic := 'X'; -- ready
rs232_0_from_uart_data : out std_logic_vector(7 downto 0); -- data
rs232_0_from_uart_error : out std_logic; -- error
rs232_0_from_uart_valid : out std_logic; -- valid
rs232_0_to_uart_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
rs232_0_to_uart_error : in std_logic := 'X'; -- error
rs232_0_to_uart_valid : in std_logic := 'X'; -- valid
rs232_0_to_uart_ready : out std_logic; -- ready
rs232_0_clk : in std_logic := 'X'; -- clk
rs232_0_UART_RXD : in std_logic := 'X'; -- RXD
rs232_0_UART_TXD : out std_logic; -- TXD
rs232_0_reset : in std_logic := 'X' -- reset
);
end component UART;

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Quartus/Design/UART/UART.html Normal file
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>datasheet for UART</title>
<style type="text/css">
body { font-family:arial ;}
a { text-decoration:underline ; color:#003000 ;}
a:hover { text-decoration:underline ; color:0030f0 ;}
td { padding : 5px ;}
table.topTitle { width:100% ;}
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
table.blueBar { width : 100% ; border-spacing : 0px ;}
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
table.blueBar td.l { text-align : left ;}
table.blueBar td.r { text-align : right ;}
table.items { width:100% ; border-collapse:collapse ;}
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ; font-size:12px ;}
body { font-family:arial ;}
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
table.x td { border:1px solid #bbb ;}
td.tableTitle { font-weight:bold ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ;}
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
.flowbox { display:inline-block ;}
.parametersbox table { font-size:10px ;}
td.parametername { font-style:italic ;}
td.parametervalue { font-weight:bold ;}
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
</head>
<body>
<table class="topTitle">
<tr>
<td class="l">UART</td>
<td class="r">
<br/>
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
<td class="l">2022.05.24.19:47:23</td>
<td class="r">Datasheet</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Overview</div>
<div class="greydiv">
<div style="display:inline-block ; text-align:left">
<table class="connectionboxes">
<tr>
<td class="lefthandwire">&#160;&#160;clk_0&#160;</td>
<td class="main" rowspan="2">UART</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
</table>
</div><span style="display:inline-block ; width:28px"> </span>
<div style="display:inline-block ; text-align:left"><span>
<br/></span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
<div class="label">Memory Map</div>
<table class="mmap">
<tr>
<td class="empty" rowspan="2"></td>
</tr>
</table>
<a name="module_clk_0"> </a>
<div>
<hr/>
<h2>clk_0</h2>clock_source v21.1
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">clockFrequency</td>
<td class="parametervalue">5000000</td>
</tr>
<tr>
<td class="parametername">clockFrequencyKnown</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">inputClockFrequency</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">resetSynchronousEdges</td>
<td class="parametervalue">NONE</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<a name="module_rs232_0"> </a>
<div>
<hr/>
<h2>rs232_0</h2>altera_up_avalon_rs232 v17.1
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">ref_clk_freq</td>
<td class="parametervalue">0.0</td>
</tr>
<tr>
<td class="parametername">avalon_bus_type</td>
<td class="parametervalue">Streaming</td>
</tr>
<tr>
<td class="parametername">baud</td>
<td class="parametervalue">115200</td>
</tr>
<tr>
<td class="parametername">parity</td>
<td class="parametervalue">None</td>
</tr>
<tr>
<td class="parametername">data_bits</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">stop_bits</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">AUTO_DEVICE_FAMILY</td>
<td class="parametervalue">CYCLONEIVE</td>
</tr>
<tr>
<td class="parametername">AUTO_CLK_CLOCK_RATE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">Cyclone IV E</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.00 seconds</td>
</tr>
</table>
</body>
</html>

293
Quartus/Design/UART/UART.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<deploy
date="2022.05.24.19:47:23"
outputDirectory="/home/ir/Documents/codelib/Quartus/Design/UART/">
<perimeter>
<parameter
name="AUTO_GENERATION_ID"
type="Integer"
defaultValue="0"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_UNIQUE_ID"
type="String"
defaultValue=""
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_FAMILY"
type="String"
defaultValue="Cyclone IV E"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE"
type="String"
defaultValue="EP4CE6E22C8"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_SPEEDGRADE"
type="String"
defaultValue="8"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_CLOCK_RATE"
type="Long"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_CLOCK_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_RESET_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_RS232_0_CLK_CLOCK_RATE"
type="Long"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_RS232_0_CLK_CLOCK_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_RS232_0_CLK_RESET_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<interface name="clk" kind="clock" start="0">
<property name="clockRate" value="5000000" />
<property name="externallyDriven" value="false" />
<property name="ptfSchematicName" value="" />
<port name="clk_clk" direction="input" role="clk" width="1" />
</interface>
<interface name="reset" kind="reset" start="0">
<property name="associatedClock" value="" />
<property name="synchronousEdges" value="NONE" />
<port name="reset_reset_n" direction="input" role="reset_n" width="1" />
</interface>
<interface
name="rs232_0_avalon_data_receive_source"
kind="avalon_streaming"
start="1">
<property name="associatedClock" value="rs232_0_clk" />
<property name="associatedReset" value="rs232_0_reset" />
<property name="beatsPerCycle" value="1" />
<property name="dataBitsPerSymbol" value="8" />
<property name="emptyWithinPacket" value="false" />
<property name="errorDescriptor" value="" />
<property name="firstSymbolInHighOrderBits" value="true" />
<property name="highOrderSymbolAtMSB" value="false" />
<property name="maxChannel" value="0" />
<property name="packetDescription" value="" />
<property name="readyLatency" value="0" />
<property name="symbolsPerBeat" value="1" />
<port
name="rs232_0_from_uart_ready"
direction="input"
role="ready"
width="1" />
<port
name="rs232_0_from_uart_data"
direction="output"
role="data"
width="8" />
<port
name="rs232_0_from_uart_error"
direction="output"
role="error"
width="1" />
<port
name="rs232_0_from_uart_valid"
direction="output"
role="valid"
width="1" />
</interface>
<interface
name="rs232_0_avalon_data_transmit_sink"
kind="avalon_streaming"
start="0">
<property name="associatedClock" value="rs232_0_clk" />
<property name="associatedReset" value="rs232_0_reset" />
<property name="beatsPerCycle" value="1" />
<property name="dataBitsPerSymbol" value="8" />
<property name="emptyWithinPacket" value="false" />
<property name="errorDescriptor" value="" />
<property name="firstSymbolInHighOrderBits" value="true" />
<property name="highOrderSymbolAtMSB" value="false" />
<property name="maxChannel" value="0" />
<property name="packetDescription" value="" />
<property name="readyLatency" value="0" />
<property name="symbolsPerBeat" value="1" />
<port name="rs232_0_to_uart_data" direction="input" role="data" width="8" />
<port name="rs232_0_to_uart_error" direction="input" role="error" width="1" />
<port name="rs232_0_to_uart_valid" direction="input" role="valid" width="1" />
<port
name="rs232_0_to_uart_ready"
direction="output"
role="ready"
width="1" />
</interface>
<interface name="rs232_0_clk" kind="clock" start="0">
<property name="clockRate" value="0" />
<property name="externallyDriven" value="false" />
<property name="ptfSchematicName" value="" />
<port name="rs232_0_clk" direction="input" role="clk" width="1" />
</interface>
<interface name="rs232_0_external_interface" kind="conduit" start="0">
<property name="associatedClock" value="" />
<property name="associatedReset" value="" />
<port name="rs232_0_UART_RXD" direction="input" role="RXD" width="1" />
<port name="rs232_0_UART_TXD" direction="output" role="TXD" width="1" />
</interface>
<interface name="rs232_0_reset" kind="reset" start="0">
<property name="associatedClock" value="rs232_0_clk" />
<property name="synchronousEdges" value="DEASSERT" />
<port name="rs232_0_reset" direction="input" role="reset" width="1" />
</interface>
</perimeter>
<entity
path=""
parameterizationKey="UART:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=EP4CE6E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1653392842,AUTO_RS232_0_CLK_CLOCK_DOMAIN=-1,AUTO_RS232_0_CLK_CLOCK_RATE=-1,AUTO_RS232_0_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(clock_source:21.1:clockFrequency=5000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_up_avalon_rs232:17.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=Cyclone IV E,avalon_bus_type=Streaming,baud=115200,data_bits=8,parity=None,ref_clk_freq=0.0,stop_bits=1)"
instancePathKey="UART"
kind="UART"
version="1.0"
name="UART">
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="AUTO_RS232_0_CLK_RESET_DOMAIN" value="-1" />
<parameter name="AUTO_GENERATION_ID" value="1653392842" />
<parameter name="AUTO_DEVICE" value="EP4CE6E22C8" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
<parameter name="AUTO_UNIQUE_ID" value="" />
<parameter name="AUTO_RS232_0_CLK_CLOCK_DOMAIN" value="-1" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
<parameter name="AUTO_RS232_0_CLK_CLOCK_RATE" value="-1" />
<generatedFiles>
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/UART.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles>
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_counters.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_sync_fifo.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/UART_rs232_0.v"
type="VERILOG" />
</childGeneratedFiles>
<sourceFiles>
<file path="/home/ir/Documents/codelib/Quartus/Design/UART.qsys" />
</sourceFiles>
<childSourceFiles>
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/altera_up_avalon_rs232_hw.tcl" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_counters.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_in_deserializer.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_out_serializer.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_sync_fifo.v" />
</childSourceFiles>
<messages>
<message level="Debug" culprit="UART">queue size: 0 starting:UART "UART"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>2</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="UART"><![CDATA["<b>UART</b>" reuses <b>altera_up_avalon_rs232</b> "<b>submodules/UART_rs232_0</b>"]]></message>
<message level="Debug" culprit="UART">queue size: 0 starting:altera_up_avalon_rs232 "submodules/UART_rs232_0"</message>
<message level="Info" culprit="rs232_0">Starting Generation of RS232 UART</message>
<message level="Error" culprit="rs232_0">The input clock frequency must be known at generation time.</message>
<message level="Info" culprit="rs232_0"><![CDATA["<b>UART</b>" instantiated <b>altera_up_avalon_rs232</b> "<b>rs232_0</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_up_avalon_rs232:17.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=Cyclone IV E,avalon_bus_type=Streaming,baud=115200,data_bits=8,parity=None,ref_clk_freq=0.0,stop_bits=1"
instancePathKey="UART:.:rs232_0"
kind="altera_up_avalon_rs232"
version="17.1"
name="UART_rs232_0">
<parameter name="baud" value="115200" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
<parameter name="stop_bits" value="1" />
<parameter name="ref_clk_freq" value="0.0" />
<parameter name="avalon_bus_type" value="Streaming" />
<parameter name="data_bits" value="8" />
<parameter name="parity" value="None" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<generatedFiles>
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_counters.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_sync_fifo.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/UART_rs232_0.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/altera_up_avalon_rs232_hw.tcl" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_counters.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_in_deserializer.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_out_serializer.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_sync_fifo.v" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="UART" as="rs232_0" />
<messages>
<message level="Debug" culprit="UART">queue size: 0 starting:altera_up_avalon_rs232 "submodules/UART_rs232_0"</message>
<message level="Info" culprit="rs232_0">Starting Generation of RS232 UART</message>
<message level="Error" culprit="rs232_0">The input clock frequency must be known at generation time.</message>
<message level="Info" culprit="rs232_0"><![CDATA["<b>UART</b>" instantiated <b>altera_up_avalon_rs232</b> "<b>rs232_0</b>"]]></message>
</messages>
</entity>
</deploy>

32
Quartus/Design/UART/UART_bb.v Normal file
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@ -0,0 +1,32 @@
module UART (
rs232_0_clk,
rs232_0_reset,
rs232_0_UART_RXD,
rs232_0_UART_TXD,
rs232_0_from_uart_ready,
rs232_0_from_uart_data,
rs232_0_from_uart_error,
rs232_0_from_uart_valid,
rs232_0_to_uart_data,
rs232_0_to_uart_error,
rs232_0_to_uart_valid,
rs232_0_to_uart_ready,
clk_clk,
reset_reset_n);
input rs232_0_clk;
input rs232_0_reset;
input rs232_0_UART_RXD;
output rs232_0_UART_TXD;
input rs232_0_from_uart_ready;
output [7:0] rs232_0_from_uart_data;
output rs232_0_from_uart_error;
output rs232_0_from_uart_valid;
input [7:0] rs232_0_to_uart_data;
input rs232_0_to_uart_error;
input rs232_0_to_uart_valid;
output rs232_0_to_uart_ready;
input clk_clk;
input reset_reset_n;
endmodule

34
Quartus/Design/UART/UART_generation.rpt Normal file
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@ -0,0 +1,34 @@
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART --family="Cyclone IV E" --part=EP4CE6E22C8
Progress: Loading Design/UART.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 21.1]
Progress: Parameterizing module clk_0
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
Progress: Parameterizing module rs232_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8
Progress: Loading Design/UART.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 21.1]
Progress: Parameterizing module clk_0
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
Progress: Parameterizing module rs232_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: UART: Generating UART "UART" for QUARTUS_SYNTH
Info: rs232_0: Starting Generation of RS232 UART
Error: rs232_0: The input clock frequency must be known at generation time.
Info: rs232_0: "UART" instantiated altera_up_avalon_rs232 "rs232_0"
Info: UART: Done "UART" with 2 modules, 6 files
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings
Info: Finished: Create HDL design files for synthesis

36
Quartus/Design/UART/UART_generation_previous.rpt Normal file
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@ -0,0 +1,36 @@
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART --family="Cyclone IV E" --part=EP4CE6E22C8
Progress: Loading Design/UART.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 21.1]
Progress: Parameterizing module clk_0
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
Progress: Parameterizing module rs232_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: UART.clk_0: The input clock frequency must be known or set by the parent if this is a subsystem.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8
Progress: Loading Design/UART.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 21.1]
Progress: Parameterizing module clk_0
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
Progress: Parameterizing module rs232_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: UART.clk_0: The input clock frequency must be known or set by the parent if this is a subsystem.
Info: UART: Generating UART "UART" for QUARTUS_SYNTH
Info: rs232_0: Starting Generation of RS232 UART
Error: rs232_0: The input clock frequency must be known at generation time.
Info: rs232_0: "UART" instantiated altera_up_avalon_rs232 "rs232_0"
Info: UART: Done "UART" with 2 modules, 6 files
Error: qsys-generate failed with exit code 1: 1 Error, 1 Warning
Info: Finished: Create HDL design files for synthesis

17
Quartus/Design/UART/UART_inst.v Normal file
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@ -0,0 +1,17 @@
UART u0 (
.rs232_0_clk (<connected-to-rs232_0_clk>), // rs232_0_clk.clk
.rs232_0_reset (<connected-to-rs232_0_reset>), // rs232_0_reset.reset
.rs232_0_UART_RXD (<connected-to-rs232_0_UART_RXD>), // rs232_0_external_interface.RXD
.rs232_0_UART_TXD (<connected-to-rs232_0_UART_TXD>), // .TXD
.rs232_0_from_uart_ready (<connected-to-rs232_0_from_uart_ready>), // rs232_0_avalon_data_receive_source.ready
.rs232_0_from_uart_data (<connected-to-rs232_0_from_uart_data>), // .data
.rs232_0_from_uart_error (<connected-to-rs232_0_from_uart_error>), // .error
.rs232_0_from_uart_valid (<connected-to-rs232_0_from_uart_valid>), // .valid
.rs232_0_to_uart_data (<connected-to-rs232_0_to_uart_data>), // rs232_0_avalon_data_transmit_sink.data
.rs232_0_to_uart_error (<connected-to-rs232_0_to_uart_error>), // .error
.rs232_0_to_uart_valid (<connected-to-rs232_0_to_uart_valid>), // .valid
.rs232_0_to_uart_ready (<connected-to-rs232_0_to_uart_ready>), // .ready
.clk_clk (<connected-to-clk_clk>), // clk.clk
.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n
);

1079
Quartus/Design/UART/synthesis/UART.debuginfo Normal file
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File diff suppressed because it is too large Load diff

48
Quartus/Design/UART/synthesis/UART.qip Normal file
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@ -0,0 +1,48 @@
set_global_assignment -entity "UART" -library "UART" -name IP_TOOL_NAME "Qsys"
set_global_assignment -entity "UART" -library "UART" -name IP_TOOL_VERSION "21.1"
set_global_assignment -entity "UART" -library "UART" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "UART" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../UART.sopcinfo"]
set_global_assignment -entity "UART" -library "UART" -name SLD_INFO "QSYS_NAME UART HAS_SOPCINFO 1 GENERATION_ID 1653392842"
set_global_assignment -library "UART" -name MISC_FILE [file join $::quartus(qip_path) "../UART.cmp"]
set_global_assignment -library "UART" -name SLD_FILE [file join $::quartus(qip_path) "UART.debuginfo"]
set_global_assignment -entity "UART" -library "UART" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E"
set_global_assignment -entity "UART" -library "UART" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -entity "UART" -library "UART" -name IP_QSYS_MODE "SYSTEM"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "UART" -name MISC_FILE [file join $::quartus(qip_path) "../../UART.qsys"]
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_NAME "VUFSVA=="
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_DISPLAY_NAME "VUFSVA=="
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY1MzM5Mjg0Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0U2RTIyQzg=::QXV0byBERVZJQ0U="
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19SUzIzMl8wX0NMS19DTE9DS19SQVRF::LTE=::QXV0byBDTE9DS19SQVRF"
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19SUzIzMl8wX0NMS19DTE9DS19ET01BSU4=::LTE=::QXV0byBDTE9DS19ET01BSU4="
set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19SUzIzMl8wX0NMS19SRVNFVF9ET01BSU4=::LTE=::QXV0byBSRVNFVF9ET01BSU4="
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_NAME "VUFSVF9yczIzMl8w"
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_DISPLAY_NAME "UlMyMzIgVUFSVA=="
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_AUTHOR "SW50ZWwgRlBHQSBVbml2ZXJzaXR5IFByb2dyYW0="
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_VERSION "MTcuMQ=="
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_DESCRIPTION "UlMyMzIgVUFSVCBDb250cm9sbGVy"
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "YXZhbG9uX2J1c190eXBl::U3RyZWFtaW5n::QXZhbG9uIFR5cGU="
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "YmF1ZA==::MTE1MjAw::QmF1ZCBSYXRlIChicHMp"
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "cGFyaXR5::Tm9uZQ==::UGFyaXR5"
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "ZGF0YV9iaXRz::OA==::RGF0YSBCaXRz"
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "c3RvcF9iaXRz::MQ==::U3RvcCBCaXRz"
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::MA==::QXV0byBDTE9DS19SQVRF"
set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "UART.v"]
set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_counters.v"]
set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_in_deserializer.v"]
set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_out_serializer.v"]
set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_sync_fifo.v"]
set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/UART_rs232_0.v"]

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// UART.v
// Generated using ACDS version 21.1 842
`timescale 1 ps / 1 ps
module UART (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
input wire rs232_0_from_uart_ready, // rs232_0_avalon_data_receive_source.ready
output wire [7:0] rs232_0_from_uart_data, // .data
output wire rs232_0_from_uart_error, // .error
output wire rs232_0_from_uart_valid, // .valid
input wire [7:0] rs232_0_to_uart_data, // rs232_0_avalon_data_transmit_sink.data
input wire rs232_0_to_uart_error, // .error
input wire rs232_0_to_uart_valid, // .valid
output wire rs232_0_to_uart_ready, // .ready
input wire rs232_0_clk, // rs232_0_clk.clk
input wire rs232_0_UART_RXD, // rs232_0_external_interface.RXD
output wire rs232_0_UART_TXD, // .TXD
input wire rs232_0_reset // rs232_0_reset.reset
);
UART_rs232_0 rs232_0 (
.clk (rs232_0_clk), // clk.clk
.reset (rs232_0_reset), // reset.reset
.from_uart_ready (rs232_0_from_uart_ready), // avalon_data_receive_source.ready
.from_uart_data (rs232_0_from_uart_data), // .data
.from_uart_error (rs232_0_from_uart_error), // .error
.from_uart_valid (rs232_0_from_uart_valid), // .valid
.to_uart_data (rs232_0_to_uart_data), // avalon_data_transmit_sink.data
.to_uart_error (rs232_0_to_uart_error), // .error
.to_uart_valid (rs232_0_to_uart_valid), // .valid
.to_uart_ready (rs232_0_to_uart_ready), // .ready
.UART_RXD (rs232_0_UART_RXD), // external_interface.export
.UART_TXD (rs232_0_UART_TXD) // .export
);
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads and writes data to the RS232 connector on Altera's *
* DE-series Development and Education Boards. *
* *
******************************************************************************/
module UART_rs232_0 (
// Inputs
clk,
reset,
from_uart_ready,
to_uart_data,
to_uart_error,
to_uart_valid,
UART_RXD,
// Bidirectionals
// Outputs
from_uart_data,
from_uart_error,
from_uart_valid,
to_uart_ready,
UART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 0; // Baud counter width
parameter BAUD_TICK_COUNT = 0;
parameter HALF_BAUD_TICK_COUNT = 0;
parameter TDW = 10; // Total data width
parameter DW = 8; // Data width
parameter ODD_PARITY = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input from_uart_ready;
input [(DW-1):0] to_uart_data;
input to_uart_error;
input to_uart_valid;
input UART_RXD;
// Bidirectionals
// Outputs
output [(DW-1):0] from_uart_data;
output from_uart_error;
output from_uart_valid;
output to_uart_ready;
output UART_TXD;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [(DW-1):0] read_data;
wire write_data_parity;
wire [ 7: 0] write_space;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign from_uart_data = read_data;
assign from_uart_error = 1'b0;
assign to_uart_ready = (|(write_space));
// Internal Assignments
assign write_data_parity = (^(to_uart_data)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_in_deserializer RS232_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.serial_data_in (UART_RXD),
.receive_data_en (from_uart_ready),
// Bidirectionals
// Outputs
.fifo_read_available (),
.received_data_valid (from_uart_valid),
.received_data (read_data)
);
defparam
RS232_In_Deserializer.CW = CW,
RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Deserializer.TDW = TDW,
RS232_In_Deserializer.DW = (DW - 1);
altera_up_rs232_out_serializer RS232_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
.transmit_data (to_uart_data),
.transmit_data_en (to_uart_valid & to_uart_ready),
// Bidirectionals
// Outputs
.fifo_write_space (write_space),
.serial_data_out (UART_TXD)
);
defparam
RS232_Out_Serializer.CW = CW,
RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Serializer.TDW = TDW,
RS232_Out_Serializer.DW = (DW - 1);
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads and writes data to the RS232 connectpr on Altera's *
* DE1 and DE2 Development and Education Boards. *
* *
******************************************************************************/
module altera_up_rs232_counters (
// Inputs
clk,
reset,
reset_counters,
// Bidirectionals
// Outputs
baud_clock_rising_edge,
baud_clock_falling_edge,
all_bits_transmitted
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // BAUD COUNTER WIDTH
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // TOTAL DATA WIDTH
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input reset_counters;
// Bidirectionals
// Outputs
output reg baud_clock_rising_edge;
output reg baud_clock_falling_edge;
output reg all_bits_transmitted;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [(CW-1):0] baud_counter;
reg [ 3: 0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
baud_counter <= {CW{1'b0}};
else if (reset_counters)
baud_counter <= {CW{1'b0}};
else if (baud_counter == BAUD_TICK_COUNT)
baud_counter <= {CW{1'b0}};
else
baud_counter <= baud_counter + 1;
end
always @(posedge clk)
begin
if (reset)
baud_clock_rising_edge <= 1'b0;
else if (baud_counter == BAUD_TICK_COUNT)
baud_clock_rising_edge <= 1'b1;
else
baud_clock_rising_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
baud_clock_falling_edge <= 1'b0;
else if (baud_counter == HALF_BAUD_TICK_COUNT)
baud_clock_falling_edge <= 1'b1;
else
baud_clock_falling_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
bit_counter <= 4'h0;
else if (reset_counters)
bit_counter <= 4'h0;
else if (bit_counter == TDW)
bit_counter <= 4'h0;
else if (baud_counter == BAUD_TICK_COUNT)
bit_counter <= bit_counter + 4'h1;
end
always @(posedge clk)
begin
if (reset)
all_bits_transmitted <= 1'b0;
else if (bit_counter == TDW)
all_bits_transmitted <= 1'b1;
else
all_bits_transmitted <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_in_deserializer (
// Inputs
clk,
reset,
serial_data_in,
receive_data_en,
// Bidirectionals
// Outputs
fifo_read_available,
received_data_valid,
received_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input serial_data_in;
input receive_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_read_available;
output received_data_valid;
output [DW: 0] received_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_received;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
// Internal Registers
reg receiving_data;
reg [(TDW-1):0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_read_available <= 8'h00;
else
fifo_read_available <= {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
receiving_data <= 1'b0;
else if (all_bits_received)
receiving_data <= 1'b0;
else if (serial_data_in == 1'b0)
receiving_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_in_shift_reg <= {TDW{1'b0}};
else if (shift_data_reg_en)
data_in_shift_reg <=
{serial_data_in, data_in_shift_reg[(TDW - 1):1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign received_data_valid = ~fifo_is_empty;
// Input assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_In_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~receiving_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (),
.baud_clock_falling_edge (shift_data_reg_en),
.all_bits_transmitted (all_bits_received)
);
defparam
RS232_In_Counters.CW = CW,
RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Counters.TDW = TDW;
altera_up_sync_fifo RS232_In_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (all_bits_received & ~fifo_is_full),
.write_data (data_in_shift_reg[(DW + 1):1]),
.read_en (receive_data_en & ~fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (received_data)
);
defparam
RS232_In_FIFO.DW = DW,
RS232_In_FIFO.DATA_DEPTH = 128,
RS232_In_FIFO.AW = 6;
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module writes data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_out_serializer (
// Inputs
clk,
reset,
transmit_data,
transmit_data_en,
// Bidirectionals
// Outputs
fifo_write_space,
serial_data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] transmit_data;
input transmit_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_write_space;
output reg serial_data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_transmitted;
wire read_fifo_en;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
wire [DW: 0] data_from_fifo;
// Internal Registers
reg transmitting_data;
reg [DW+1:0] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_write_space <= 8'h00;
else
fifo_write_space <= 8'h80 - {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
serial_data_out <= 1'b1;
else
serial_data_out <= data_out_shift_reg[0];
end
always @(posedge clk)
begin
if (reset)
transmitting_data <= 1'b0;
else if (all_bits_transmitted)
transmitting_data <= 1'b0;
else if (fifo_is_empty == 1'b0)
transmitting_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_out_shift_reg <= {(DW + 2){1'b1}};
else if (read_fifo_en)
data_out_shift_reg <= {data_from_fifo, 1'b0};
else if (shift_data_reg_en)
data_out_shift_reg <=
{1'b1, data_out_shift_reg[DW+1:1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign read_fifo_en =
~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_Out_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~transmitting_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (shift_data_reg_en),
.baud_clock_falling_edge (),
.all_bits_transmitted (all_bits_transmitted)
);
defparam
RS232_Out_Counters.CW = CW,
RS232_Out_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Counters.TDW = TDW;
altera_up_sync_fifo RS232_Out_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (transmit_data_en & ~fifo_is_full),
.write_data (transmit_data),
.read_en (read_fifo_en),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (data_from_fifo)
);
defparam
RS232_Out_FIFO.DW = DW,
RS232_Out_FIFO.DATA_DEPTH = 128,
RS232_Out_FIFO.AW = 6;
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data)
// Unused
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 19:36:33 五月 24, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "21.1"
DATE = "19:36:33 五月 24, 2022"
# Revisions
PROJECT_REVISION = "design"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 19:36:33 五月 24, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# design_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY design
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:36:33 五月 24, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name QSYS_FILE uart_screen.qsys
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_FILE design.v

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uart_screen u0 (
.clk_clk (<connected-to-clk_clk>), // clk.clk
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
.rs232_0_from_uart_ready (<connected-to-rs232_0_from_uart_ready>), // rs232_0_avalon_data_receive_source.ready
.rs232_0_from_uart_data (<connected-to-rs232_0_from_uart_data>), // .data
.rs232_0_from_uart_error (<connected-to-rs232_0_from_uart_error>), // .error
.rs232_0_from_uart_valid (<connected-to-rs232_0_from_uart_valid>), // .valid
.rs232_0_to_uart_data (<connected-to-rs232_0_to_uart_data>), // rs232_0_avalon_data_transmit_sink.data
.rs232_0_to_uart_error (<connected-to-rs232_0_to_uart_error>), // .error
.rs232_0_to_uart_valid (<connected-to-rs232_0_to_uart_valid>), // .valid
.rs232_0_to_uart_ready (<connected-to-rs232_0_to_uart_ready>), // .ready
.rs232_0_UART_RXD (<connected-to-rs232_0_UART_RXD>), // rs232_0_external_interface.RXD
.rs232_0_UART_TXD (<connected-to-rs232_0_UART_TXD>) // .TXD
);

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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element clk_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element rs232_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE6E22C8" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="8" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="avalon_rs232_slave" internal="rs232_0.avalon_rs232_slave" />
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface name="interrupt" internal="rs232_0.interrupt" />
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
<interface
name="rs232_0_avalon_data_receive_source"
internal="rs232_0.avalon_data_receive_source"
type="avalon_streaming"
dir="start">
<port name="rs232_0_from_uart_ready" internal="from_uart_ready" />
<port name="rs232_0_from_uart_data" internal="from_uart_data" />
<port name="rs232_0_from_uart_error" internal="from_uart_error" />
<port name="rs232_0_from_uart_valid" internal="from_uart_valid" />
</interface>
<interface
name="rs232_0_avalon_data_transmit_sink"
internal="rs232_0.avalon_data_transmit_sink"
type="avalon_streaming"
dir="end">
<port name="rs232_0_to_uart_data" internal="to_uart_data" />
<port name="rs232_0_to_uart_error" internal="to_uart_error" />
<port name="rs232_0_to_uart_valid" internal="to_uart_valid" />
<port name="rs232_0_to_uart_ready" internal="to_uart_ready" />
</interface>
<interface
name="rs232_0_external_interface"
internal="rs232_0.external_interface"
type="conduit"
dir="end">
<port name="rs232_0_UART_RXD" internal="UART_RXD" />
<port name="rs232_0_UART_TXD" internal="UART_TXD" />
</interface>
<module name="clk_0" kind="clock_source" version="21.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module
name="rs232_0"
kind="altera_up_avalon_rs232"
version="17.1"
enabled="1"
autoexport="1">
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="avalon_bus_type" value="Streaming" />
<parameter name="baud" value="115200" />
<parameter name="data_bits" value="8" />
<parameter name="parity" value="None" />
<parameter name="stop_bits" value="1" />
</module>
<connection kind="clock" version="21.1" start="clk_0.clk" end="rs232_0.clk" />
<connection
kind="reset"
version="21.1"
start="clk_0.clk_reset"
end="rs232_0.reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>

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# (C) 2001-2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files from any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License Subscription
# Agreement, Intel FPGA IP License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Intel and sold by
# Intel or its authorized distributors. Please refer to the applicable
# agreement for further details.
# +---------------------------------------------------
# | Cut the async clear paths
# +---------------------------------------------------
set aclr_counter 0
set clrn_counter 0
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
set aclr_counter [get_collection_size $aclr_collection]
set clrn_counter [get_collection_size $clrn_collection]
if {$aclr_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
}
if {$clrn_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
}

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/21.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2020/06/22 $
// $Author: psgswbuild $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/21.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2020/06/22 $
// $Author: psgswbuild $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads and writes data to the RS232 connectpr on Altera's *
* DE1 and DE2 Development and Education Boards. *
* *
******************************************************************************/
module altera_up_rs232_counters (
// Inputs
clk,
reset,
reset_counters,
// Bidirectionals
// Outputs
baud_clock_rising_edge,
baud_clock_falling_edge,
all_bits_transmitted
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // BAUD COUNTER WIDTH
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // TOTAL DATA WIDTH
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input reset_counters;
// Bidirectionals
// Outputs
output reg baud_clock_rising_edge;
output reg baud_clock_falling_edge;
output reg all_bits_transmitted;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [(CW-1):0] baud_counter;
reg [ 3: 0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
baud_counter <= {CW{1'b0}};
else if (reset_counters)
baud_counter <= {CW{1'b0}};
else if (baud_counter == BAUD_TICK_COUNT)
baud_counter <= {CW{1'b0}};
else
baud_counter <= baud_counter + 1;
end
always @(posedge clk)
begin
if (reset)
baud_clock_rising_edge <= 1'b0;
else if (baud_counter == BAUD_TICK_COUNT)
baud_clock_rising_edge <= 1'b1;
else
baud_clock_rising_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
baud_clock_falling_edge <= 1'b0;
else if (baud_counter == HALF_BAUD_TICK_COUNT)
baud_clock_falling_edge <= 1'b1;
else
baud_clock_falling_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
bit_counter <= 4'h0;
else if (reset_counters)
bit_counter <= 4'h0;
else if (bit_counter == TDW)
bit_counter <= 4'h0;
else if (baud_counter == BAUD_TICK_COUNT)
bit_counter <= bit_counter + 4'h1;
end
always @(posedge clk)
begin
if (reset)
all_bits_transmitted <= 1'b0;
else if (bit_counter == TDW)
all_bits_transmitted <= 1'b1;
else
all_bits_transmitted <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_in_deserializer (
// Inputs
clk,
reset,
serial_data_in,
receive_data_en,
// Bidirectionals
// Outputs
fifo_read_available,
received_data_valid,
received_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input serial_data_in;
input receive_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_read_available;
output received_data_valid;
output [DW: 0] received_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_received;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
// Internal Registers
reg receiving_data;
reg [(TDW-1):0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_read_available <= 8'h00;
else
fifo_read_available <= {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
receiving_data <= 1'b0;
else if (all_bits_received)
receiving_data <= 1'b0;
else if (serial_data_in == 1'b0)
receiving_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_in_shift_reg <= {TDW{1'b0}};
else if (shift_data_reg_en)
data_in_shift_reg <=
{serial_data_in, data_in_shift_reg[(TDW - 1):1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign received_data_valid = ~fifo_is_empty;
// Input assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_In_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~receiving_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (),
.baud_clock_falling_edge (shift_data_reg_en),
.all_bits_transmitted (all_bits_received)
);
defparam
RS232_In_Counters.CW = CW,
RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Counters.TDW = TDW;
altera_up_sync_fifo RS232_In_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (all_bits_received & ~fifo_is_full),
.write_data (data_in_shift_reg[(DW + 1):1]),
.read_en (receive_data_en & ~fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (received_data)
);
defparam
RS232_In_FIFO.DW = DW,
RS232_In_FIFO.DATA_DEPTH = 128,
RS232_In_FIFO.AW = 6;
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module writes data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_out_serializer (
// Inputs
clk,
reset,
transmit_data,
transmit_data_en,
// Bidirectionals
// Outputs
fifo_write_space,
serial_data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] transmit_data;
input transmit_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_write_space;
output reg serial_data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_transmitted;
wire read_fifo_en;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
wire [DW: 0] data_from_fifo;
// Internal Registers
reg transmitting_data;
reg [DW+1:0] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_write_space <= 8'h00;
else
fifo_write_space <= 8'h80 - {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
serial_data_out <= 1'b1;
else
serial_data_out <= data_out_shift_reg[0];
end
always @(posedge clk)
begin
if (reset)
transmitting_data <= 1'b0;
else if (all_bits_transmitted)
transmitting_data <= 1'b0;
else if (fifo_is_empty == 1'b0)
transmitting_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_out_shift_reg <= {(DW + 2){1'b1}};
else if (read_fifo_en)
data_out_shift_reg <= {data_from_fifo, 1'b0};
else if (shift_data_reg_en)
data_out_shift_reg <=
{1'b1, data_out_shift_reg[DW+1:1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign read_fifo_en =
~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_Out_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~transmitting_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (shift_data_reg_en),
.baud_clock_falling_edge (),
.all_bits_transmitted (all_bits_transmitted)
);
defparam
RS232_Out_Counters.CW = CW,
RS232_Out_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Counters.TDW = TDW;
altera_up_sync_fifo RS232_Out_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (transmit_data_en & ~fifo_is_full),
.write_data (transmit_data),
.read_en (read_fifo_en),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (data_from_fifo)
);
defparam
RS232_Out_FIFO.DW = DW,
RS232_Out_FIFO.DATA_DEPTH = 128,
RS232_Out_FIFO.AW = 6;
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data)
// Unused
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule

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// (C) 2001-2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads and writes data to the RS232 connector on Altera's *
* DE-series Development and Education Boards. *
* *
******************************************************************************/
module uart_screen_rs232_0 (
// Inputs
clk,
reset,
from_uart_ready,
to_uart_data,
to_uart_error,
to_uart_valid,
UART_RXD,
// Bidirectionals
// Outputs
from_uart_data,
from_uart_error,
from_uart_valid,
to_uart_ready,
UART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 434;
parameter HALF_BAUD_TICK_COUNT = 217;
parameter TDW = 10; // Total data width
parameter DW = 8; // Data width
parameter ODD_PARITY = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input from_uart_ready;
input [(DW-1):0] to_uart_data;
input to_uart_error;
input to_uart_valid;
input UART_RXD;
// Bidirectionals
// Outputs
output [(DW-1):0] from_uart_data;
output from_uart_error;
output from_uart_valid;
output to_uart_ready;
output UART_TXD;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [(DW-1):0] read_data;
wire write_data_parity;
wire [ 7: 0] write_space;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign from_uart_data = read_data;
assign from_uart_error = 1'b0;
assign to_uart_ready = (|(write_space));
// Internal Assignments
assign write_data_parity = (^(to_uart_data)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_in_deserializer RS232_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.serial_data_in (UART_RXD),
.receive_data_en (from_uart_ready),
// Bidirectionals
// Outputs
.fifo_read_available (),
.received_data_valid (from_uart_valid),
.received_data (read_data)
);
defparam
RS232_In_Deserializer.CW = CW,
RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Deserializer.TDW = TDW,
RS232_In_Deserializer.DW = (DW - 1);
altera_up_rs232_out_serializer RS232_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
.transmit_data (to_uart_data),
.transmit_data_en (to_uart_valid & to_uart_ready),
// Bidirectionals
// Outputs
.fifo_write_space (write_space),
.serial_data_out (UART_TXD)
);
defparam
RS232_Out_Serializer.CW = CW,
RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Serializer.TDW = TDW,
RS232_Out_Serializer.DW = (DW - 1);
endmodule

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84
Quartus/Design/uart_screen/synthesis/uart_screen.qip Normal file
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set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL_NAME "Qsys"
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL_VERSION "21.1"
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "uart_screen" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../uart_screen.sopcinfo"]
set_global_assignment -entity "uart_screen" -library "uart_screen" -name SLD_INFO "QSYS_NAME uart_screen HAS_SOPCINFO 1 GENERATION_ID 1653392990"
set_global_assignment -library "uart_screen" -name MISC_FILE [file join $::quartus(qip_path) "../uart_screen.cmp"]
set_global_assignment -library "uart_screen" -name SLD_FILE [file join $::quartus(qip_path) "uart_screen.debuginfo"]
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E"
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_QSYS_MODE "SYSTEM"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "uart_screen" -name MISC_FILE [file join $::quartus(qip_path) "../../uart_screen.qsys"]
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_NAME "dWFydF9zY3JlZW4="
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_DISPLAY_NAME "dWFydF9zY3JlZW4="
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY1MzM5Mjk5MA==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0U2RTIyQzg=::QXV0byBERVZJQ0U="
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_NAME "YWx0ZXJhX3Jlc2V0X2NvbnRyb2xsZXI="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_DISPLAY_NAME "TWVybGluIFJlc2V0IENvbnRyb2xsZXI="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_VERSION "MjEuMQ=="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_DESCRIPTION "Rm9yIHN5c3RlbXMgd2l0aCBtdWx0aXBsZSByZXNldCBpbnB1dHMsIHRoZSBNZXJsaW4gUmVzZXQgQ29udHJvbGxlciBPUnMgYWxsIHJlc2V0IGlucHV0cyBhbmQgZ2VuZXJhdGVzIGEgc2luZ2xlIHJlc2V0IG91dHB1dC4="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "TlVNX1JFU0VUX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIGlucHV0cw=="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "T1VUUFVUX1JFU0VUX1NZTkNfRURHRVM=::ZGVhc3NlcnQ=::T3V0cHV0IFJlc2V0IFN5bmNocm9ub3VzIEVkZ2Vz"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "U1lOQ19ERVBUSA==::Mg==::U3luY2hyb25pemVyIGRlcHRo"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRVUVTVF9QUkVTRU5U::MA==::UmVzZXQgcmVxdWVzdCBsb2dpYyBlbmFibGU="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRX1dBSVRfVElNRQ==::MQ==::UmVzZXQgcmVxdWVzdCB3YWl0IHRpbWU="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "TUlOX1JTVF9BU1NFUlRJT05fVElNRQ==::Mw==::TWluaW11bSByZXNldCBhc3NlcnRpb24gdGltZQ=="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRX0VBUkxZX0RTUlRfVElNRQ==::MQ==::UmVzZXQgcmVxdWVzdCBkZWFzc2VydCB0aW1pbmc="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4w::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjA="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4x::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4y::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjI="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4z::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjM="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU40::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjQ="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU41::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjU="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU42::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjY="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU43::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjc="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU44::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjg="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU45::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjk="
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMA==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEw"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMQ==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEx"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMg==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEy"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMw==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEz"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xNA==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE0"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xNQ==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE1"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU5QVVQ=::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcmVzZXRfaW5wdXRz"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QURBUFRfUkVTRVRfUkVRVUVTVA==::MA==::T25seSBhZGFwdCBvbmx5IHJlc2V0IHJlcXVlc3Q="
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_NAME "dWFydF9zY3JlZW5fcnMyMzJfMA=="
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_DISPLAY_NAME "UlMyMzIgVUFSVA=="
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_AUTHOR "SW50ZWwgRlBHQSBVbml2ZXJzaXR5IFByb2dyYW0="
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_VERSION "MTcuMQ=="
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_DESCRIPTION "UlMyMzIgVUFSVCBDb250cm9sbGVy"
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "YXZhbG9uX2J1c190eXBl::U3RyZWFtaW5n::QXZhbG9uIFR5cGU="
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "YmF1ZA==::MTE1MjAw::QmF1ZCBSYXRlIChicHMp"
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "cGFyaXR5::Tm9uZQ==::UGFyaXR5"
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "ZGF0YV9iaXRz::OA==::RGF0YSBCaXRz"
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "c3RvcF9iaXRz::MQ==::U3RvcCBCaXRz"
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "uart_screen.v"]
set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"]
set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_synchronizer.v"]
set_global_assignment -library "uart_screen" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.sdc"]
set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_counters.v"]
set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_in_deserializer.v"]
set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_out_serializer.v"]
set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_sync_fifo.v"]
set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/uart_screen_rs232_0.v"]
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_TOOL_NAME "altera_reset_controller"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_TOOL_VERSION "21.1"
set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_TOOL_ENV "Qsys"

101
Quartus/Design/uart_screen/synthesis/uart_screen.v Normal file
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@ -0,0 +1,101 @@
// uart_screen.v
// Generated using ACDS version 21.1 842
`timescale 1 ps / 1 ps
module uart_screen (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
input wire rs232_0_from_uart_ready, // rs232_0_avalon_data_receive_source.ready
output wire [7:0] rs232_0_from_uart_data, // .data
output wire rs232_0_from_uart_error, // .error
output wire rs232_0_from_uart_valid, // .valid
input wire [7:0] rs232_0_to_uart_data, // rs232_0_avalon_data_transmit_sink.data
input wire rs232_0_to_uart_error, // .error
input wire rs232_0_to_uart_valid, // .valid
output wire rs232_0_to_uart_ready, // .ready
input wire rs232_0_UART_RXD, // rs232_0_external_interface.RXD
output wire rs232_0_UART_TXD // .TXD
);
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> rs232_0:reset
uart_screen_rs232_0 rs232_0 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.from_uart_ready (rs232_0_from_uart_ready), // avalon_data_receive_source.ready
.from_uart_data (rs232_0_from_uart_data), // .data
.from_uart_error (rs232_0_from_uart_error), // .error
.from_uart_valid (rs232_0_from_uart_valid), // .valid
.to_uart_data (rs232_0_to_uart_data), // avalon_data_transmit_sink.data
.to_uart_error (rs232_0_to_uart_error), // .error
.to_uart_valid (rs232_0_to_uart_valid), // .valid
.to_uart_ready (rs232_0_to_uart_ready), // .ready
.UART_RXD (rs232_0_UART_RXD), // external_interface.export
.UART_TXD (rs232_0_UART_TXD) // .export
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule

149
Quartus/Design/uart_screen/uart_screen.bsf Normal file
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@ -0,0 +1,149 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2021 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 544 288)
(text "uart_screen" (rect 237 -1 285 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 272 20 284)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 224 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 224 112)(line_width 1))
)
(port
(pt 544 72)
(input)
(text "rs232_0_from_uart_ready" (rect 0 0 109 12)(font "Arial" (font_size 8)))
(text "rs232_0_from_uart_ready" (rect 410 61 548 72)(font "Arial" (font_size 8)))
(line (pt 544 72)(pt 304 72)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "rs232_0_to_uart_data[7..0]" (rect 0 0 109 12)(font "Arial" (font_size 8)))
(text "rs232_0_to_uart_data[7..0]" (rect 4 141 160 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 224 152)(line_width 3))
)
(port
(pt 0 168)
(input)
(text "rs232_0_to_uart_error" (rect 0 0 93 12)(font "Arial" (font_size 8)))
(text "rs232_0_to_uart_error" (rect 4 157 130 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 224 168)(line_width 1))
)
(port
(pt 0 184)
(input)
(text "rs232_0_to_uart_valid" (rect 0 0 90 12)(font "Arial" (font_size 8)))
(text "rs232_0_to_uart_valid" (rect 4 173 130 184)(font "Arial" (font_size 8)))
(line (pt 0 184)(pt 224 184)(line_width 1))
)
(port
(pt 0 240)
(input)
(text "rs232_0_UART_RXD" (rect 0 0 95 12)(font "Arial" (font_size 8)))
(text "rs232_0_UART_RXD" (rect 4 229 100 240)(font "Arial" (font_size 8)))
(line (pt 0 240)(pt 224 240)(line_width 1))
)
(port
(pt 544 88)
(output)
(text "rs232_0_from_uart_data[7..0]" (rect 0 0 122 12)(font "Arial" (font_size 8)))
(text "rs232_0_from_uart_data[7..0]" (rect 393 77 561 88)(font "Arial" (font_size 8)))
(line (pt 544 88)(pt 304 88)(line_width 3))
)
(port
(pt 544 104)
(output)
(text "rs232_0_from_uart_error" (rect 0 0 106 12)(font "Arial" (font_size 8)))
(text "rs232_0_from_uart_error" (rect 414 93 552 104)(font "Arial" (font_size 8)))
(line (pt 544 104)(pt 304 104)(line_width 1))
)
(port
(pt 544 120)
(output)
(text "rs232_0_from_uart_valid" (rect 0 0 103 12)(font "Arial" (font_size 8)))
(text "rs232_0_from_uart_valid" (rect 416 109 554 120)(font "Arial" (font_size 8)))
(line (pt 544 120)(pt 304 120)(line_width 1))
)
(port
(pt 0 200)
(output)
(text "rs232_0_to_uart_ready" (rect 0 0 96 12)(font "Arial" (font_size 8)))
(text "rs232_0_to_uart_ready" (rect 4 189 130 200)(font "Arial" (font_size 8)))
(line (pt 0 200)(pt 224 200)(line_width 1))
)
(port
(pt 0 256)
(output)
(text "rs232_0_UART_TXD" (rect 0 0 93 12)(font "Arial" (font_size 8)))
(text "rs232_0_UART_TXD" (rect 4 245 100 256)(font "Arial" (font_size 8)))
(line (pt 0 256)(pt 224 256)(line_width 1))
)
(drawing
(text "clk" (rect 209 43 436 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 229 67 476 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 195 83 420 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 229 107 500 224)(font "Arial" (color 0 0 0)))
(text "rs232_0_avalon_data_receive_source" (rect 305 43 814 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "ready" (rect 276 67 582 144)(font "Arial" (color 0 0 0)))
(text "data" (rect 283 83 590 176)(font "Arial" (color 0 0 0)))
(text "error" (rect 279 99 588 208)(font "Arial" (color 0 0 0)))
(text "valid" (rect 281 115 592 240)(font "Arial" (color 0 0 0)))
(text "rs232_0_avalon_data_transmit_sink" (rect 11 123 220 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "data" (rect 229 147 482 304)(font "Arial" (color 0 0 0)))
(text "error" (rect 229 163 488 336)(font "Arial" (color 0 0 0)))
(text "valid" (rect 229 179 488 368)(font "Arial" (color 0 0 0)))
(text "ready" (rect 229 195 488 400)(font "Arial" (color 0 0 0)))
(text "rs232_0_external_interface" (rect 64 211 284 435)(font "Arial" (color 128 0 0)(font_size 9)))
(text "RXD" (rect 229 235 476 480)(font "Arial" (color 0 0 0)))
(text "TXD" (rect 229 251 476 512)(font "Arial" (color 0 0 0)))
(text " uart_screen " (rect 489 272 1056 554)(font "Arial" ))
(line (pt 224 32)(pt 304 32)(line_width 1))
(line (pt 304 32)(pt 304 272)(line_width 1))
(line (pt 224 272)(pt 304 272)(line_width 1))
(line (pt 224 32)(pt 224 272)(line_width 1))
(line (pt 225 52)(pt 225 76)(line_width 1))
(line (pt 226 52)(pt 226 76)(line_width 1))
(line (pt 225 92)(pt 225 116)(line_width 1))
(line (pt 226 92)(pt 226 116)(line_width 1))
(line (pt 303 52)(pt 303 124)(line_width 1))
(line (pt 302 52)(pt 302 124)(line_width 1))
(line (pt 225 132)(pt 225 204)(line_width 1))
(line (pt 226 132)(pt 226 204)(line_width 1))
(line (pt 225 220)(pt 225 260)(line_width 1))
(line (pt 226 220)(pt 226 260)(line_width 1))
(line (pt 0 0)(pt 544 0)(line_width 1))
(line (pt 544 0)(pt 544 288)(line_width 1))
(line (pt 0 288)(pt 544 288)(line_width 1))
(line (pt 0 0)(pt 0 288)(line_width 1))
)
)

17
Quartus/Design/uart_screen/uart_screen.cmp Normal file
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component uart_screen is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
rs232_0_from_uart_ready : in std_logic := 'X'; -- ready
rs232_0_from_uart_data : out std_logic_vector(7 downto 0); -- data
rs232_0_from_uart_error : out std_logic; -- error
rs232_0_from_uart_valid : out std_logic; -- valid
rs232_0_to_uart_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
rs232_0_to_uart_error : in std_logic := 'X'; -- error
rs232_0_to_uart_valid : in std_logic := 'X'; -- valid
rs232_0_to_uart_ready : out std_logic; -- ready
rs232_0_UART_RXD : in std_logic := 'X'; -- RXD
rs232_0_UART_TXD : out std_logic -- TXD
);
end component uart_screen;

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>datasheet for uart_screen</title>
<style type="text/css">
body { font-family:arial ;}
a { text-decoration:underline ; color:#003000 ;}
a:hover { text-decoration:underline ; color:0030f0 ;}
td { padding : 5px ;}
table.topTitle { width:100% ;}
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
table.blueBar { width : 100% ; border-spacing : 0px ;}
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
table.blueBar td.l { text-align : left ;}
table.blueBar td.r { text-align : right ;}
table.items { width:100% ; border-collapse:collapse ;}
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ; font-size:12px ;}
body { font-family:arial ;}
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
table.x td { border:1px solid #bbb ;}
td.tableTitle { font-weight:bold ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ;}
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
.flowbox { display:inline-block ;}
.parametersbox table { font-size:10px ;}
td.parametername { font-style:italic ;}
td.parametervalue { font-weight:bold ;}
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
</head>
<body>
<table class="topTitle">
<tr>
<td class="l">uart_screen</td>
<td class="r">
<br/>
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
<td class="l">2022.05.24.19:49:50</td>
<td class="r">Datasheet</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Overview</div>
<div class="greydiv">
<div style="display:inline-block ; text-align:left">
<table class="connectionboxes">
<tr>
<td class="lefthandwire">&#160;&#160;clk_0&#160;</td>
<td class="main" rowspan="2">uart_screen</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
</table>
</div><span style="display:inline-block ; width:28px"> </span>
<div style="display:inline-block ; text-align:left"><span>
<br/></span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
<div class="label">Memory Map</div>
<table class="mmap">
<tr>
<td class="empty" rowspan="2"></td>
</tr>
</table>
<a name="module_clk_0"> </a>
<div>
<hr/>
<h2>clk_0</h2>clock_source v21.1
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">clockFrequency</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">clockFrequencyKnown</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">inputClockFrequency</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">resetSynchronousEdges</td>
<td class="parametervalue">NONE</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<a name="module_rs232_0"> </a>
<div>
<hr/>
<h2>rs232_0</h2>altera_up_avalon_rs232 v17.1
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="4">
<a href="#module_clk_0">clk_0</a>
</td>
<td class="from">clk&#160;&#160;</td>
<td class="main" rowspan="4">rs232_0</td>
</tr>
<tr>
<td class="to">&#160;&#160;clk</td>
</tr>
<tr>
<td class="from">clk_reset&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset</td>
</tr>
</table>
</div>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">ref_clk_freq</td>
<td class="parametervalue">5.0E7</td>
</tr>
<tr>
<td class="parametername">avalon_bus_type</td>
<td class="parametervalue">Streaming</td>
</tr>
<tr>
<td class="parametername">baud</td>
<td class="parametervalue">115200</td>
</tr>
<tr>
<td class="parametername">parity</td>
<td class="parametervalue">None</td>
</tr>
<tr>
<td class="parametername">data_bits</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">stop_bits</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">AUTO_DEVICE_FAMILY</td>
<td class="parametervalue">CYCLONEIVE</td>
</tr>
<tr>
<td class="parametername">AUTO_CLK_CLOCK_RATE</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">Cyclone IV E</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.03 seconds</td>
</tr>
</table>
</body>
</html>

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Quartus/Design/uart_screen/uart_screen.ppf Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<pinplan
variation_name="rs232_0"
megafunction_name="ALTERA_UP_AVALON_RS232"
intended_family="Cyclone IV E"
specifies="all_ports">
<global>
<pin name="clk" direction="input" scope="external" />
<pin name="reset" direction="input" scope="external" />
<pin name="from_uart_ready" direction="input" scope="external" />
<pin name="from_uart_data[7..0]" direction="output" scope="external" />
<pin name="from_uart_error" direction="output" scope="external" />
<pin name="from_uart_valid" direction="output" scope="external" />
<pin name="to_uart_data[7..0]" direction="input" scope="external" />
<pin name="to_uart_error" direction="input" scope="external" />
<pin name="to_uart_valid" direction="input" scope="external" />
<pin name="to_uart_ready" direction="output" scope="external" />
<pin name="UART_RXD" direction="input" scope="external" />
<pin name="UART_TXD" direction="output" scope="external" />
</global>
</pinplan>

313
Quartus/Design/uart_screen/uart_screen.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<deploy
date="2022.05.24.19:49:50"
outputDirectory="/home/ir/Documents/codelib/Quartus/Design/uart_screen/">
<perimeter>
<parameter
name="AUTO_GENERATION_ID"
type="Integer"
defaultValue="0"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_UNIQUE_ID"
type="String"
defaultValue=""
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_FAMILY"
type="String"
defaultValue="Cyclone IV E"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE"
type="String"
defaultValue="EP4CE6E22C8"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_SPEEDGRADE"
type="String"
defaultValue="8"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_CLOCK_RATE"
type="Long"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_CLOCK_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_RESET_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<interface name="clk" kind="clock" start="0">
<property name="clockRate" value="50000000" />
<property name="externallyDriven" value="false" />
<property name="ptfSchematicName" value="" />
<port name="clk_clk" direction="input" role="clk" width="1" />
</interface>
<interface name="reset" kind="reset" start="0">
<property name="associatedClock" value="" />
<property name="synchronousEdges" value="NONE" />
<port name="reset_reset_n" direction="input" role="reset_n" width="1" />
</interface>
<interface
name="rs232_0_avalon_data_receive_source"
kind="avalon_streaming"
start="1">
<property name="associatedClock" value="clk" />
<property name="associatedReset" value="reset" />
<property name="beatsPerCycle" value="1" />
<property name="dataBitsPerSymbol" value="8" />
<property name="emptyWithinPacket" value="false" />
<property name="errorDescriptor" value="" />
<property name="firstSymbolInHighOrderBits" value="true" />
<property name="highOrderSymbolAtMSB" value="false" />
<property name="maxChannel" value="0" />
<property name="packetDescription" value="" />
<property name="readyLatency" value="0" />
<property name="symbolsPerBeat" value="1" />
<port
name="rs232_0_from_uart_ready"
direction="input"
role="ready"
width="1" />
<port
name="rs232_0_from_uart_data"
direction="output"
role="data"
width="8" />
<port
name="rs232_0_from_uart_error"
direction="output"
role="error"
width="1" />
<port
name="rs232_0_from_uart_valid"
direction="output"
role="valid"
width="1" />
</interface>
<interface
name="rs232_0_avalon_data_transmit_sink"
kind="avalon_streaming"
start="0">
<property name="associatedClock" value="clk" />
<property name="associatedReset" value="reset" />
<property name="beatsPerCycle" value="1" />
<property name="dataBitsPerSymbol" value="8" />
<property name="emptyWithinPacket" value="false" />
<property name="errorDescriptor" value="" />
<property name="firstSymbolInHighOrderBits" value="true" />
<property name="highOrderSymbolAtMSB" value="false" />
<property name="maxChannel" value="0" />
<property name="packetDescription" value="" />
<property name="readyLatency" value="0" />
<property name="symbolsPerBeat" value="1" />
<port name="rs232_0_to_uart_data" direction="input" role="data" width="8" />
<port name="rs232_0_to_uart_error" direction="input" role="error" width="1" />
<port name="rs232_0_to_uart_valid" direction="input" role="valid" width="1" />
<port
name="rs232_0_to_uart_ready"
direction="output"
role="ready"
width="1" />
</interface>
<interface name="rs232_0_external_interface" kind="conduit" start="0">
<property name="associatedClock" value="" />
<property name="associatedReset" value="" />
<port name="rs232_0_UART_RXD" direction="input" role="RXD" width="1" />
<port name="rs232_0_UART_TXD" direction="output" role="TXD" width="1" />
</interface>
</perimeter>
<entity
path=""
parameterizationKey="uart_screen:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=EP4CE6E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1653392990,AUTO_UNIQUE_ID=(clock_source:21.1:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_up_avalon_rs232:17.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone IV E,avalon_bus_type=Streaming,baud=115200,data_bits=8,parity=None,ref_clk_freq=5.0E7,stop_bits=1)(clock:21.1:)(reset:21.1:)"
instancePathKey="uart_screen"
kind="uart_screen"
version="1.0"
name="uart_screen">
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="AUTO_GENERATION_ID" value="1653392990" />
<parameter name="AUTO_DEVICE" value="EP4CE6E22C8" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
<parameter name="AUTO_UNIQUE_ID" value="" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
<generatedFiles>
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/uart_screen.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles>
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_counters.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_in_deserializer.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_out_serializer.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_up_sync_fifo.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.v"
type="VERILOG"
attributes="" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_synchronizer.v"
type="VERILOG"
attributes="" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.sdc"
type="SDC"
attributes="" />
</childGeneratedFiles>
<sourceFiles>
<file path="/home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys" />
</sourceFiles>
<childSourceFiles>
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/altera_up_avalon_rs232_hw.tcl" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_counters.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_in_deserializer.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_out_serializer.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_sync_fifo.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
</childSourceFiles>
<messages>
<message level="Debug" culprit="uart_screen">queue size: 0 starting:uart_screen "uart_screen"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>2</b> modules, <b>2</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug" culprit="reset_adaptation_transform"><![CDATA[After transform: <b>3</b> modules, <b>4</b> connections]]></message>
<message level="Debug" culprit="uart_screen"><![CDATA["<b>uart_screen</b>" reuses <b>altera_up_avalon_rs232</b> "<b>submodules/uart_screen_rs232_0</b>"]]></message>
<message level="Debug" culprit="uart_screen"><![CDATA["<b>uart_screen</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
<message level="Debug" culprit="uart_screen">queue size: 1 starting:altera_up_avalon_rs232 "submodules/uart_screen_rs232_0"</message>
<message level="Info" culprit="rs232_0">Starting Generation of RS232 UART</message>
<message level="Info" culprit="rs232_0"><![CDATA["<b>uart_screen</b>" instantiated <b>altera_up_avalon_rs232</b> "<b>rs232_0</b>"]]></message>
<message level="Debug" culprit="uart_screen">queue size: 0 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
<message level="Info" culprit="rst_controller"><![CDATA["<b>uart_screen</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_up_avalon_rs232:17.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone IV E,avalon_bus_type=Streaming,baud=115200,data_bits=8,parity=None,ref_clk_freq=5.0E7,stop_bits=1"
instancePathKey="uart_screen:.:rs232_0"
kind="altera_up_avalon_rs232"
version="17.1"
name="uart_screen_rs232_0">
<parameter name="baud" value="115200" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
<parameter name="stop_bits" value="1" />
<parameter name="ref_clk_freq" value="5.0E7" />
<parameter name="avalon_bus_type" value="Streaming" />
<parameter name="data_bits" value="8" />
<parameter name="parity" value="None" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<generatedFiles>
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_counters.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_in_deserializer.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_out_serializer.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_up_sync_fifo.v"
type="VERILOG" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/altera_up_avalon_rs232_hw.tcl" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_counters.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_in_deserializer.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_out_serializer.v" />
<file
path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_sync_fifo.v" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="uart_screen" as="rs232_0" />
<messages>
<message level="Debug" culprit="uart_screen">queue size: 1 starting:altera_up_avalon_rs232 "submodules/uart_screen_rs232_0"</message>
<message level="Info" culprit="rs232_0">Starting Generation of RS232 UART</message>
<message level="Info" culprit="rs232_0"><![CDATA["<b>uart_screen</b>" instantiated <b>altera_up_avalon_rs232</b> "<b>rs232_0</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_reset_controller:21.1:ADAPT_RESET_REQUEST=0,MIN_RST_ASSERTION_TIME=3,NUM_RESET_INPUTS=1,OUTPUT_RESET_SYNC_EDGES=deassert,RESET_REQUEST_PRESENT=0,RESET_REQ_EARLY_DSRT_TIME=1,RESET_REQ_WAIT_TIME=1,SYNC_DEPTH=2,USE_RESET_REQUEST_IN0=0,USE_RESET_REQUEST_IN1=0,USE_RESET_REQUEST_IN10=0,USE_RESET_REQUEST_IN11=0,USE_RESET_REQUEST_IN12=0,USE_RESET_REQUEST_IN13=0,USE_RESET_REQUEST_IN14=0,USE_RESET_REQUEST_IN15=0,USE_RESET_REQUEST_IN2=0,USE_RESET_REQUEST_IN3=0,USE_RESET_REQUEST_IN4=0,USE_RESET_REQUEST_IN5=0,USE_RESET_REQUEST_IN6=0,USE_RESET_REQUEST_IN7=0,USE_RESET_REQUEST_IN8=0,USE_RESET_REQUEST_IN9=0,USE_RESET_REQUEST_INPUT=0"
instancePathKey="uart_screen:.:rst_controller"
kind="altera_reset_controller"
version="21.1"
name="altera_reset_controller">
<generatedFiles>
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.v"
type="VERILOG"
attributes="" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_synchronizer.v"
type="VERILOG"
attributes="" />
<file
path="/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.sdc"
type="SDC"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="/opt/intelFPGA/21.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="uart_screen" as="rst_controller" />
<messages>
<message level="Debug" culprit="uart_screen">queue size: 0 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
<message level="Info" culprit="rst_controller"><![CDATA["<b>uart_screen</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
</messages>
</entity>
</deploy>

28
Quartus/Design/uart_screen/uart_screen_bb.v Normal file
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@ -0,0 +1,28 @@
module uart_screen (
rs232_0_UART_RXD,
rs232_0_UART_TXD,
rs232_0_from_uart_ready,
rs232_0_from_uart_data,
rs232_0_from_uart_error,
rs232_0_from_uart_valid,
rs232_0_to_uart_data,
rs232_0_to_uart_error,
rs232_0_to_uart_valid,
rs232_0_to_uart_ready,
clk_clk,
reset_reset_n);
input rs232_0_UART_RXD;
output rs232_0_UART_TXD;
input rs232_0_from_uart_ready;
output [7:0] rs232_0_from_uart_data;
output rs232_0_from_uart_error;
output rs232_0_from_uart_valid;
input [7:0] rs232_0_to_uart_data;
input rs232_0_to_uart_error;
input rs232_0_to_uart_valid;
output rs232_0_to_uart_ready;
input clk_clk;
input reset_reset_n;
endmodule

34
Quartus/Design/uart_screen/uart_screen_generation.rpt Normal file
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@ -0,0 +1,34 @@
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen --family="Cyclone IV E" --part=EP4CE6E22C8
Progress: Loading Design/uart_screen.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 21.1]
Progress: Parameterizing module clk_0
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
Progress: Parameterizing module rs232_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8
Progress: Loading Design/uart_screen.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 21.1]
Progress: Parameterizing module clk_0
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
Progress: Parameterizing module rs232_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: uart_screen: Generating uart_screen "uart_screen" for QUARTUS_SYNTH
Info: rs232_0: Starting Generation of RS232 UART
Info: rs232_0: "uart_screen" instantiated altera_up_avalon_rs232 "rs232_0"
Info: rst_controller: "uart_screen" instantiated altera_reset_controller "rst_controller"
Info: uart_screen: Done "uart_screen" with 3 modules, 9 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

30
Quartus/Design/uart_screen/uart_screen_generation_previous.rpt Normal file
View file

@ -0,0 +1,30 @@
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen --family="Cyclone IV E" --part=EP4CE6E22C8
Progress: Loading Design/uart_screen.qsys
Progress: Reading input file
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
Progress: Parameterizing module rs232_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8
Progress: Loading Design/uart_screen.qsys
Progress: Reading input file
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
Progress: Parameterizing module rs232_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: uart_screen: Generating uart_screen "uart_screen" for QUARTUS_SYNTH
Info: rs232_0: Starting Generation of RS232 UART
Error: rs232_0: The input clock frequency must be known at generation time.
Info: rs232_0: "uart_screen" instantiated altera_up_avalon_rs232 "rs232_0"
Info: uart_screen: Done "uart_screen" with 2 modules, 6 files
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings
Info: Finished: Create HDL design files for synthesis

15
Quartus/Design/uart_screen/uart_screen_inst.v Normal file
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@ -0,0 +1,15 @@
uart_screen u0 (
.rs232_0_UART_RXD (<connected-to-rs232_0_UART_RXD>), // rs232_0_external_interface.RXD
.rs232_0_UART_TXD (<connected-to-rs232_0_UART_TXD>), // .TXD
.rs232_0_from_uart_ready (<connected-to-rs232_0_from_uart_ready>), // rs232_0_avalon_data_receive_source.ready
.rs232_0_from_uart_data (<connected-to-rs232_0_from_uart_data>), // .data
.rs232_0_from_uart_error (<connected-to-rs232_0_from_uart_error>), // .error
.rs232_0_from_uart_valid (<connected-to-rs232_0_from_uart_valid>), // .valid
.rs232_0_to_uart_data (<connected-to-rs232_0_to_uart_data>), // rs232_0_avalon_data_transmit_sink.data
.rs232_0_to_uart_error (<connected-to-rs232_0_to_uart_error>), // .error
.rs232_0_to_uart_valid (<connected-to-rs232_0_to_uart_valid>), // .valid
.rs232_0_to_uart_ready (<connected-to-rs232_0_to_uart_ready>), // .ready
.clk_clk (<connected-to-clk_clk>), // clk.clk
.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n
);